Integrated circuit memory devices such as DRAM devices are widely used in consumer and industrial products. As is well known to those having skill in the art integrated circuit memory devices include an array of memory cells that are generally arranged in rows and columns. It will be understood that as used herein, rows and columns are used to identify relative directions in an array of memory cells rather than an absolute horizontal or vertical direction. Data is written into and read from selected memory cells using peripheral circuits including decoders and control circuits. The array of memory cells may also be arranged in a plurality of subarray blocks, each having rows and columns.
As the integration density and speed of integrated circuit memory devices continue to increase, efforts have been made to decrease the size of the individual memory cells. Moreover, efforts have also been made to more efficiently lay out or arrange the peripheral circuits in the integrated circuit, so that more of the integrated circuit area may be occupied by memory cells rather than peripheral circuits.
FIG. 1 illustrates a conventional layout of an integrated circuit memory device 400 such as a 16 Megabit DRAM, in an integrated circuit such as a semiconductor substrate 410. The integrated circuit is also referred to as a chip. Referring to FIG. 1, a plurality of subarray blocks 7a, 7b, . . . , 7t of memory cells are grouped into four groups of subarray blocks in a cell area of the integrated circuit 410. The portion of the integrated circuit outside the memory cells is also referred to as a peripheral circuit area.
The peripheral circuit area includes pad layers 1a and 1b arranged transversely at the center of the integrated circuit, subarray block control circuits 6a and 6c, 6b and 6d arranged symmetrically on opposite sides of the pad layers 1a and 1b respectively, and row decoders 5a and 5c, 5b and 5d arranged symmetrically on opposite sides and remote from the pad layers 1a and 1b respectively. The peripheral circuit area also includes column decoders 9a and 9c, 9b and 9d longitudinally arranged symmetrically adjacent inner edges of the pad layers 1a and 1b respectively, buffer and control circuits 2a and 2b, 2c and 2d arranged between the column decoders 9a and 9b, 9c and 9d respectively, a column redundancy circuit 4a and a row redundancy circuit 3a arranged between the buffer and control circuits 2a and 2b, and a column redundancy circuit 4b and a row redundancy circuit 3b arranged between the buffer and control circuits 2c and 2d.
An area designated by a reference numeral 80, includes a bit line sense amplifier for sensing and amplifying a potential difference between a bit line connected to a selected memory cell and a reference bit line. The area 80 also includes an array select switching circuit for deactivating one block when one of the adjacent subarray blocks is activated so that the sense amplifier may be shared by the adjacent subarray blocks, and an input/output gate circuit for gating input/output of data.
The pad layers 1a and 1b include a plurality of pads that can be wire-bonded to a lead frame. Each pad supplies an external power source, or can receive and/or transmit various external input and output signals, respectively. The external input and output signals can include control signals for a read/write operation, read data or write data. The various control signals can include address signals, a row address strobe signal and a column address strobe signal. These various control signals are applied to the buffer and control circuits 2a, 2b, 2c and 2d through the pad layers 1a and 1b. The buffer and control circuits 2a, 2b, 2c and 2d include an input/output buffer, a control buffer and an address buffer. The buffer and control circuits 2a, 2b, 2c and 2d multiplex applied address signals to latch the multiplexed signals to the address buffer as row and column addresses, and supply read data stored in the input/output buffer to external of the memory device.
For column and row redundancy operations, the column redundancy circuits 4a and 4b and the row redundancy circuits 3a and 3b include column and row fuse boxes each having a plurality of fuses such as polysilicon fuses that can be cut or trimmed, for example by laser or current. The row redundancy operation deactivates a normal word line selected by decoding row address signals and activates a corresponding spare word line. The normal word line is replaced with the spare word line in order to repair a defective memory cell connected to the normal word line by use of a redundancy memory cell. The column redundancy operation deactivates a normal bit line selected by decoding column address signals and activates a corresponding spare bit line. The row redundancy circuits 3a and 3b each generally includes a row fuse box, and the column redundancy circuits 4a and 4b each generally includes a column fuse box. The total size of the column fuse box may be about one quarter of that of the row fuse box.
The row decoders 5a, 5c, 5b and 5d are arranged adjacent the cell region and generate a select signal to designate one of a plurality of word lines by decoding the applied row addresses. The applied row addresses may be generated from a row address buffer located within the buffer and control circuits 2a, 2b, 2c and 2d and from a row predecoder for predecoding a part of the row addresses. The word lines are connected to a plurality of memory cells belonging to the same row.
The subarray block control circuits 6a, 6c, 6b and 6d control the subarray blocks 7a, 7b, . . . , 7t to read data from the memory cells and to write data into the memory cells. In more detail, the subarray block control circuits 6a, 6c, 6b and 6d receive row and column addresses, control the operation of the sense amplifier connected to a bit line and a data bus line in a read operating mode, and control a write driver in a write operating mode. The subarray blocks 7a, 7b, . . . 7t include a plurality of memory cells, each of which may include one access transistor and one storage capacitor. The memory cells are arranged in an array or matrix of rows and columns. The gate of a transistor may be connected to a word line and the drain thereof may be connected to a bit line. Other memory cell configurations may also be used.
FIG. 2 illustrates a more detailed layout of row redundancy circuits shown in FIG. 1. FIG. 2 shows about half the layout of the integrated circuit memory device 400 of FIG. 1. When turning the drawing of FIG. 1 counterclockwise by 90.degree., the layout of the fuse boxes within the row redundancy circuits may be seen. Referring to FIG. 2, one pad layer 1a of the pad layers 1a and 1b shown in FIG. 1 is illustrated at the center of the drawing. The subarray block control circuit 6a indicated in FIG. 1 is divided into two circuits 6ai and 6aj to the left of the pad layer 1a. Similarly, the subarray block control circuit 6c depicted in FIG. 1 is arranged as two circuits 6ci and 6cj to the right of the pad layer 1a. When including three subarray blocks 7e, 7d and 7c as indicated in FIG. 1, the row decoder 5a is divided into three row decoders 5ai, 5aj and 5ak, and the row decoder 5c is divided into three row decoders 5ci, 5cj and 5ck. Since the layout of FIG. 2 is a symmetric structure centering on the pad layer 1a, the layout of the left of the pad layer 1a generally will be described hereinafter.
The column decoder 9a, and the subarray blocks 7e, 7d and 7c are identical to those shown in FIG. 1. The respective subarray blocks 7e, 7d and 7c include a redundancy cell block 7sp having a plurality of redundancy memory cells. An array select switching circuit 80a, a sense amplifier 80b, an input/output gate circuit 80c and an array select switching circuit 80d are arranged within the area 80 shown in FIG. 1 between the subarray blocks 7e and 7d. An array select switching circuit 80e, a sense amplifier 80f, an input/output gate circuit 80g and an array select switching circuit 80h are arranged within the area 80 between the subarray blocks 7d and 7c. A fuse box 3ai situated within the row redundancy circuit 3a shown in FIG. 1 includes a plurality of fuses such as polysilicon fuses therein and may be about four times as large as the column fuse box.
Redundancy enable signals REDi-REDn that are generated through output buses of the fuse box 3ai, are respectively supplied to the row decoders 5ai, 5aj and 5ak. Address signals AO-A11 that are generated through the pad layer 1a are applied to a row predecoder 21a. Predecoding row addresses DRAi-DRAn that are generated through output buses of the row predecoder 21a, are supplied to the row decoders 5al, 5aj and 5ak and to the fuse box 3ai.
The buses for transferring the redundancy enable signals REDi-REDn and the buses for transferring the predecoding row addresses DRAi-DRAn intersect at an area A. These buses are arranged on different layers of the integrated circuit in order to electrically isolate each other at the upper portion of a word line layer. Therefore, the size of the area A may impact the overall size of the integrated circuit. Moreover, since the buses for transferring the redundancy enable signals REDi-REDn are positioned at an area B, the integrated circuit memory may increase in size due to the number of the bus lines and the width thereof. Furthermore, since part of the buses for transferring the redundancy enable signals REDi-REDn may be connected to the row decoder 5ak which is remote, bus line loading may increase during operation of the device. Although the predecoding row addresses DRAi-DRAn generated from the row predecoder 21a are directly applied to the row decoders, they may be applied to the fuse box 3ai through other buses. Hence, the area occupied by the buses may increase.
Accordingly, a conventional layout as described above may increase the size of the integrated circuit and the bus line loading. Hence, an improved layout which can reduce the size of the integrated circuit and reduce the bus line loading would be desirable.